Switching regulators, phase-looked loops, delay-locked loops are vitally important devices. Switching regulators are building blocks used extensively in power systems, industry, motor, communication, networks, digital systems, consumer electronics, computers, and any other fields that high efficient voltage regulating functions. Phase-looked loops and delay-locked loops are building blocks used extensively in communication, networks, digital systems, consumer electronics, computers, and any other fields that require frequency synthesizing and synchronization.
Switching regulators (i.e., DC-TO-DC converters) can provide output voltages which can be less than, greater than, or of opposite polarity to the input voltage. Prior Art FIG. 1 illustrates a basic architecture of a conventional switching regulator 100. The conventional switching regulator 100 basically consists of an oscillator, a reference circuit, an error amplifier, a modulator including a comparator, resistors, and a control logic circuit. Control technique of switching regulators has typically used two modulators: a pulse-width modulator and a pulse-frequency modulator. The output dc level is sensed through the feedback loop including two resistors. An error amplifier compares this sampled output voltage and the reference voltage. The output of the error amplifier is compared against a periodic ramp generated by the saw tooth oscillator. The pulse-width modulator output passes through the control logic to the high voltage power switch. The feedback system regulates the current transfer to maintain a constant voltage within the load limits. In other words, it insures that the output voltage comes into regulation. However, it takes a long time until the regulated output reaches the equilibrium after the system starts. Since a power supply of a core processor is connected to one of the outputs of switching regulators in most system applications, even the core processor should stand by until it receives the regulated output from the switching regulator, too. Therefore, unfortunately, the conventional switching regulator 100 can not be efficiently implemented in system-on-chip (SOC), integrated circuit (IC), monolithic circuit, and discrete circuit since power and time are wasted until the output voltage of the switching regulator comes into regulation. In most switching regulator applications, it is highly desirable to control all switching regulators to start differently according to power sequence such as core-up-first and core-down-last. In addition, the slow start-up of the switching regulator increases design simulation time.
Thus, what is desperately needed is a cost-effective switching regulator that can attain a short controllable start-up time with an improvement in productivity, cost, chip area, power consumption, and design time. The present invention satisfies these needs by providing controllable idle time current mirror circuits utilizing a current mirror and a sensing gate, too.
The phase-looked loop is a very versatile building block suitable for a variety of frequency synthesis, clock recovery, and synchronization applications. Prior Art FIG. 2 illustrates a basic architecture of a conventional phase-locked loop. The conventional phase-locked loop 200 typically consists of a phase-frequency detector (or a phase detector), a charge-pump, a low-pass filter, a voltage-controlled oscillator, and a frequency divider in a loop. However, to understand phase-locked loops, phase-locked loops without any frequency dividers in a loop will be considered here. The phase-frequency detector (or a phase detector) is a block that has an output voltage with an average value proportional to the phase difference between the input signal and the output of the voltage-controlled oscillator. The charge-pump either injects the charge into the low-pass filter or subtracts the charge from the low-pass filter, depending on the outputs of the phase-frequency detector (or a phase detector). Therefore, change in the low-pass filter's output voltage is used to drive the voltage-controlled oscillator. The negative feedback of the loop results in the output of the voltage-controlled oscillator being synchronized with the input signal. As a result, the phase-locked loop is in lock.
In the conventional phase-locked loop of Prior Art FIG. 2, lock-in time is defined as the time that is required to attain lock from an initial loop condition. Assuming that the phase-locked loop bandwidth is fixed, the lock-in time is proportional to the initial difference frequency between the initial input signal frequency and the voltage-controlled oscillator's frequency as follows:
            (                        ω          in                -                  ω          osc                    )        2        ω    0    3  where ωin is the input signal frequency, ωosc is the voltage-controlled oscillator's frequency, and ω0 is the loop bandwidth. It should be noted that the lock-in time depends upon a loop bandwidth. If the loop bandwidth of a phase-locked loop is very wide, the lock-in time is very fast.
Most systems require different types of switching regulators, different types of phase-looked loops, and different types of delay-looked loops, which must be integrated on the same chip or board. For example, if two different phase-locked loops which have different bandwidths are used together on the same chip or board, they will result in different lock-in times. In addition, if an output signal of a phase-looked loop is assumed to be used as the input signal of another phase-looked loop, the output signal can not be accurate until both phase-looked loops are locked. Most reliable systems require a fast controllable lock-in time so that different phase-looked loops are locked quickly and synchronously. However, the conventional phase-locked loops including Prior Art FIG. 2 have recently suffered from slow uncontrollable lock-in time in most system applications. As a result, time and power of phase-looked loops are unnecessarily consumed because they are all slow-locking phase-locked loops. In addition, a conventional fast-locking phase-locked loop of Prior Art FIG. 3 is illustrated to overcome the slow-locking problem. The conventional fast-locking phase-locked loop consists of a digital phase-frequency detector including a 6-bit counter, a proportional-integral controller, a 10-bit digital-to-analog converter, and a voltage-controlled oscillator. Unfortunately, the conventional fast-locking phase-locked loop 300 is costly, complicated, and inefficient because additional blocks such as proportional-integral controller and 10-bit digital-to-analog converter take much more chip area and consume much more power. The conventional fast-locking phase-locked loop of Prior Art FIG. 3 has following disadvantages: requirement of complicated stability analysis, bad productivity, higher cost, larger chip area, much more power consumption, and longer design time. In addition, the conventional fast-locking phase-locked loop 300 of Prior Art FIG. 3 can not provide controllable lock-in time. Therefore, the conventional fast-locking phase-locked loop 300 can not be widely implemented in system-on-chip (SOC), integrated circuit (IC), monolithic integrated circuit, and discrete circuit.
Thus, what is desperately needed is a cost-effective phase-locked loop that can attain a fast controllable lock-in time with an improvement in all aspects. The present invention satisfies these needs by providing the controllable idle time current mirror circuits.
Delay-looked loops are typically employed for the purpose of synchronization. Prior Art FIG. 4 illustrates a basic architecture of a conventional delay-locked loop. A conventional delay-locked loop 400 typically consists of a phase detector, a charge-pump, a loop filter, and a voltage-controlled delay line. In delay-locked loops, the phase detector is a block that has an output voltage with an average value proportional to the phase difference between the input signal clock and the output clock at the end of delay line. The charge-pump either injects the charge into the loop filter or subtracts the charge from the loop filter, depending on the outputs of the phase detector. Therefore, change in the loop filter's output voltage will affect the delay time of the voltage-controlled delay line. If delay different from integer multiples of clock period is detected, the closed delay-locked loop will automatically correct it by changing the delay time of the voltage-controlled delay line.
It was just stated that most recent systems require different types of switching regulators, different types of phase-looked loops, and different types of delay-looked loops which must be integrated on the same chip or board. For example, if two delay-locked loops which have different bandwidths are used together, they will result in different lock-in times. In particular, if an output signal of a phase-looked loop is assumed to be used as the input signal of a delay-looked loop, the output signal of the delay-looked loop can not be accurate until the phase-locked loop are locked. Most reliable systems require a fast controllable lock-in time so that both phase-looked loops and delay-looked loops are locked synchronously and quickly. However, most conventional delay locked-loops including the conventional delay locked-loop 400 have suffered from slow-locking, harmonic locking, and uncontrollable locking. As a result, time and power of delay-looked loops are unnecessarily consumed until the delay-locked loops are locked. To overcome the slow-locking problem, a conventional fast-locking delay-locked loop of Prior Art FIG. 5 is illustrated. The conventional fast-locking delay-locked loop 500 basically consists of an analog phase detector, a charge-pump, a loop filter, a voltage-controlled delay lines, a digital phase detector, a 2-bit successive-approximation register (SAR), and a DCDL. Unfortunately, the conventional fast-locking delay-locked loop 500 is costly, complicated, and inefficient to be implemented in system-on-chip (SOC), integrated circuit (IC), monolithic circuit, and discrete circuit because additional blocks such as DCDL and 2-bit successive-approximation register (SAR) take much more chip area and consume much more power. In addition, the conventional fast-locking delay-locked loop of Prior Art FIG. 5 might improve the lock-in time, but certainly results in the following penalties: uncontrollable lock-in time, bad productivity, higher cost, larger chip area, much more power consumption, and longer design time. Thus, the conventional fast-locking delay-locked loop 500 can not be widely implemented in system-on-chip (SOC), integrated circuit (IC), monolithic circuit, and discrete circuit.
Thus, what is desperately needed is a cost-effective delay-locked loop that can attain a fast controllable lock-in time with an improvement in productivity, cost, chip area, power consumption, and design time. At the same time, what is desperately needed is a cost-effective circuit that enables both phase-locked loops and delay-locked loops to achieve fast controllable lock-in time, and enables switching regulator to achieve a short controllable start-up time with an improvement in all aspects. Lock-in time of phase-locked loops or start-up time of switching regulators can be termed “idle time”. The present invention satisfies these needs by providing controllable idle time current mirror circuits, too.
In summary, unfortunately the conventional switching regulator 100 of Prior Art FIG. 1, the conventional phase-locked loop 200 of Prior Art FIG. 2, the conventional fast-locking phase-locked loop 300 of Prior Art FIG. 3, the conventional delay-locked loop 400 of Prior Art FIG. 4, and the conventional fast-locking delay-locked loop 500 of Prior Art FIG. 5 are very inefficient to be implemented in system-on-chip (SOC), integrated circuit (IC), monolithic circuit, and discrete circuit. In addition, those integrated circuits 100, 200, 300, 400, and 500 have taken a long time to be simulated and verified before they are fabricated. Also, many other additional drawbacks are described as follows: First, the conventional phase-locked loops 200 and conventional delay-locked loop 400 have suffered from a very long time required to attain lock. Hence, time and power are unnecessarily consumed until the conventional phase-locked loop 200 or the conventional delay-locked loop 400 is in lock. Second, the conventional phase-locked loop 200 has suffered from harmonic locking and the conventional delay-locked loop 400 has suffered from failing to lock. Especially harmonic locking is that the phase-locked loop locks to harmonics of the input signal when a multiplier is used for the phase detector. Third, the conventional switching regulator 100 has suffered from long time to require the output voltage to be regulated. Fourth, simulation time in designing these integrated circuits is absolutely proportional to time required the loops to lock, time to require the output voltage of the switching regulators to be regulated, and number of blocks to be designed and verified. Hence, this long simulation time adds additional cost to the integrated circuit (IC) and serious bottleneck to design time-to-market. Fifth, the conventional locked loops and the conventional switching regulators do not have common analog building block to reduce the number of different blocks that need to be designed and verified. As a result, regularity and productivity can not be achieved. Sixth, the conventional fast-locking phase-locked loop 300 and conventional fast-locking delay-locked loop 500 might improve the lock-in time, but definitely results in uncontrollable lock-in time, bad productivity, higher cost, larger chip area, much more power consumption, and longer design time. Seventh, since lock-in time of phase-locked loops and delay-locked loops and start-up time of switching regulator take different time due to uncontrollable idle time, power and time of most systems are unnecessarily consumed until all systems are in lock or come into regulation and thus power-management of most systems can not be performed.
Thus, what is finally needed is a cost-effective circuit that can make a fast controllable lock-in time for phase-locked loops and delay-locked loops, make a short controllable start-up time for switching regulators, manage power and time consumption for all systems until loops are in lock or until the output voltage of switching regulators comes into regulation, reduce significantly design time for better time-to-market, and improve productivity by reusing the same cost-effective circuit design for the systems such as switching regulators, phase-locked loops, and delay-locked loops to be implemented in system-on chip (SOC), integrated circuit, monolithic circuits, and discrete circuit. The present invention satisfies these needs by providing four embodiments.